GATES
Module
module gatesm(a, b, c);
input a;
input b;
output [6:0] c;
and(c[0],a,b);
or(c[1],a,b);
not(c[2],a);
nand(c[3],a,b);
nor(c[4],a,b);
xor(c[5],a,b);
xnor(c[6],a,b);
endmodule
TEST BENCH
module gatest_v;
reg a;
reg b;
wire [6:0] c;
gatesm uut (
.a(a),
.b(b),
.c(c)
);
initial begin
#10 a=1'b0;b=1'b0;
#10 a=1'b0;b=1'b1;
#10 a=1'b1;b=1'b0;
#10 a=1'b1;b=1'b1;
#10$stop;
end
endmodule
OUTPUT
HALF ADDER
Module
module halfadderm(a, b, sum, carry);
input a;
input b;
output sum;
output carry;
assign carry=a&b;
assign sum=a^b;
endmodule
TEST BENCH
module halfaddert_v;
reg a;
reg b;
wire sum;
wire carry;
halfadderm uut (
.a(a),
.b(b),
.sum(sum),
.carry(carry)
);
initial begin
#10 a=1'b0;b=1'b0;
#10 a=1'b0;b=1'b1;
#10 a=1'b1;b=1'b0;
#10 a=1'b1;b=1'b1;
#10$stop;
end
endmodule
OUTPUT
HALF SUBRACTOR
Module
module halfsub(a, b, dif, borrow);
input a;
input b;
output dif;
output borrow;
wire a_;
xor(dif,a,b);
not(a_,a);
and(borrow,a_,b);
endmodule
TEST BENCH
module halfsubt_v;
reg a;
reg b;
wire dif;
wire borrow;
halfsub uut (
.a(a),
.b(b),
.dif(dif),
.borrow(borrow)
);
initial begin
#10 a=1'b0;b=1'b0;
#10 a=1'b0;b=1'b1;
#10 a=1'b1;b=1'b0;
#10 a=1'b1;b=1'b1;
#10$stop;
end
endmodule
OUTPUT
FULL ADDER
Module
module fulladdm(a, b, c, sum, carry);
input a;
input b;
input c;
output sum;
output carry;
wire d,e,f;
xor(sum,a,b,c);
and(d,a,b);
and(e,b,c);
and(f,a,c);
or(carry,d,e,f);
endmodule
TEST BENCH
module fulladdt_v;
reg a;
reg b;
reg c;
wire sum;
wire carry;
fulladdm uut (
.a(a),
.b(b),
.c(c),
.sum(sum),
.carry(carry)
);
initial begin
#10 a=1'b0;b=1'b0;c=1'b0;
#10 a=1'b0;b=1'b0;c=1'b1;
#10 a=1'b0;b=1'b1;c=1'b0;
#10 a=1'b0;b=1'b1;c=1'b1;
#10 a=1'b1;b=1'b0;c=1'b0;
#10 a=1'b1;b=1'b0;c=1'b1;
#10 a=1'b1;b=1'b1;c=1'b0;
#10 a=1'b1;b=1'b1;c=1'b1;
#10$stop;
end
endmodule
OUTPUT
FULL SUBRACTOR
Module
module fullsub(a, b, c, borrow, dif);
input a;
input b;
input c;
output borrow;
output dif;
wire d,e,f;
xor(dif,a,b,c);
and(d,~a,b);
and(e,b,c);
and(f,~a,c);
or(borrow,d,e,f);
endmodule
TEST BENCH
module fullsubt_v;
reg a;
reg b;
reg c;
wire borrow;
wire dif;
fullsub uut (
.a(a),
.b(b),
.c(c),
.borrow(borrow),
.dif(dif)
);
initial begin
#10 a=1'b0;b=1'b0;c=1'b0;
#10 a=1'b0;b=1'b0;c=1'b1;
#10 a=1'b0;b=1'b1;c=1'b0;
#10 a=1'b0;b=1'b1;c=1'b1;
#10 a=1'b1;b=1'b0;c=1'b0;
#10 a=1'b1;b=1'b0;c=1'b1;
#10 a=1'b1;b=1'b1;c=1'b0;
#10 a=1'b1;b=1'b1;c=1'b1;
#10$stop;
end
endmodule
OUTPUT
MUX
Module
module muxm(a, s, o);
input [3:0] a;
input [1:0] s;
output o;
reg o;
always @(a or s)
begin
case (s)
2'b00:o=a[0];
2'b01:o=a[1];
2'b10:o=a[2];
2'b11:o=a[3];
default:o=0;
endcase
end
endmodule
TEST BENCH
module muxt_v;
reg [3:0] a;
reg [1:0] s;
wire o;
muxm uut (
.a(a),
.s(s),
.o(o)
);
initial begin
#10 a=4'b1010;
#10 s=2'b00;
#10 s=2'b01;
#10 s=2'b10;
#10 s=2'b11;
#10 $stop;
end
endmodule
OUTPUT
DEMUX
Module
module demuxm(s,a,d);
input [0:1] s;
input a;
output [0:3] d;
reg [0:3] d;
always @(a or s)
begin
if(a==1)
begin
case (s)
2'b00:d=4'b1000;
2'b01:d=4'b0100;
2'b10:d=4'b0010;
2'b11:d=4'b0001;
default:d=0;
endcase
end else if(a==0)
d=0;
end
endmodule
TEST BENCH
module demuxt_v;
reg [0:1] s;
reg a;
wire [0:3] d;
demuxm uut (
.s(s),
.a(a),
.d(d)
);
initial begin
#10 s=2'b00;a=1'b0;
#10 s=2'b00;a=1'b1;
#10 s=2'b01;a=1'b0;
#10 s=2'b01;a=1'b1;
#10 s=2'b10;a=1'b0;
#10 s=2'b10;a=1'b1;
#10 s=2'b11;a=1'b0;
#10 s=2'b11;a=1'b1;
#10 $stop;
end
endmodule
OUTPUT
ENCODER
Module
module encoderm(d, a, b, c);
input [0:7] d;
output a;
output b;
output c;
or(a,d[4],d[5],d[6],d[7]);
or(b,d[3],d[2],d[6],d[7]);
or(c,d[1],d[3],d[5],d[7]);
endmodule
TEST BENCH
module encodert_v;
reg [0:7] d;
wire a;
wire b;
wire c;
encoderm uut (
.d(d),
.a(a),
.b(b),
.c(c)
);
initial begin
#10 d=8'b10000000;
#10 d=8'b01000000;
#10 d=8'b00100000;
#10 d=8'b00010000;
#10 d=8'b00001000;
#10 d=8'b00000100;
#10 d=8'b00000010;
#10 d=8'b00000001;
#10$stop;
end
endmodule
OUTPUT
DECODER
Module
module decoderm(e, a, b, d);
input e;
input a;
input b;
output [7:0] d;
assign d[0]=(~e)&(~a)&(~b);
assign d[1]=(~e)&(~a)&(b);
assign d[2]=(~e)&(a)&(~b);
assign d[3]=(~e)&(a)&(b);
assign d[4]=(e)&(~a)&(~b);
assign d[5]=(e)&(~a)&(b);
assign d[6]=(e)&(a)&(~b);
assign d[7]=(e)&(a)&(b);
endmodule
TEST BENCH
module decodert_v;
reg e;
reg a;
reg b;
wire [7:0] d;
decoderm uut (
.e(e),
.a(a),
.b(b),
.d(d)
);
initial begin
#10 e=1'b0;a=1'b0;b=1'b0;
#10 e=1'b0;a=1'b0;b=1'b1;
#10 e=1'b0;a=1'b1;b=1'b0;
#10 e=1'b0;a=1'b1;b=1'b1;
#10 e=1'b1;a=1'b0;b=1'b0;
#10 e=1'b1;a=1'b0;b=1'b1;
#10 e=1'b1;a=1'b1;b=1'b0;
#10 e=1'b1;a=1'b1;b=1'b1;
#10$stop;
end
endmodule
TEST BENCH
ADDER
Module
module adderm(a, b, sum, carry);
input [7:0] a;
input [7:0] b;
output [7:0] sum;
output carry;
wire[8:0]temp;
assign temp=(a+b);
assign sum=temp[7:0];
assign carry=temp[8];
endmodule
TEST BENCH
module addert_v;
reg [7:0] a;
reg [7:0] b;
wire [7:0] sum;
wire carry;
adderm uut (
.a(a),
.b(b),
.sum(sum),
.carry(carry)
);
initial begin
#10 a=8'b10000001;b=8'b00001000;
#10 a=8'b10000000;b=8'b10000000;
#10 a=8'b00000111;b=8'b00111000;
#10 a=8'b11111111;b=8'b00000001;
#10$stop;
end
endmodule
OUTPUT
MULTIPLIER
Module
module multiplierm(a, b, out);
input [4:0] a;
input [4:0] b;
output [9:0] out;
assign out=(a*b);
endmodule
TEST BENCH
module multipliert_v;
reg [4:0] a;
reg [4:0] b;
wire [9:0] out;
multiplierm uut (
.a(a),
.b(b),
.out(out)
);
initial begin
#10 a=4'b1000;b=4'b0010;
#10 a=4'b0010;b=4'b0010;
#10 a=4'b0100;b=4'b0100;
#10 a=4'b1000;b=4'b0001;
#10$stop;
end
endmodule
OUTPUT
8 BIT RIPPLE CARRY ADDER
Module
module ripple(a, b, cin, sum, cout);
input [07:0] a;
input [07:0] b;
input cin;
output [7:0]sum;
output cout;
wire[6:0] c;
fulladd a1(a[0],b[0],cin,sum[0],c[0]);
fulladd a2(a[1],b[1],c[0],sum[1],c[1]);
fulladd a3(a[2],b[2],c[1],sum[2],c[2]);
fulladd a4(a[3],b[3],c[2],sum[3],c[3]);
fulladd a5(a[4],b[4],c[3],sum[4],c[4]);
fulladd a6(a[5],b[5],c[4],sum[5],c[5]);
fulladd a7(a[6],b[6],c[5],sum[6],c[6]);
fulladd a8(a[7],b[7],c[6],sum[7],cout);
endmodule
/////////////////////////////////////////////////////////////////////////////////////////////////////////////
module fulladd(a, b, cin, sum, cout);
input a;
input b;
input cin;
output sum;
output cout;
assign sum=(a^b^cin);
assign cout=((a&b)|(b&cin)|(a&cin));
endmodule
//////////////////////////////////////////////////////////////////////////////////////////////////////////////
TEST BENCH
module rippleadder_v;
reg [7:0] a;
reg [7:0] b;
reg cin;
wire [7:0] sum;
wire cout;
ripple uut (
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.cout(cout)
);
initial begin
#10 a=8'b00000001;b=8'b00000001;cin=1'b0;
#10 a=8'b00000001;b=8'b00000001;cin=1'b1;
#10 a=8'b00000010;b=8'b00000011;cin=1'b0;
#10 a=8'b10000001;b=8'b10000001;cin=1'b0;
#10 a=8'b00011001;b=8'b00110001;cin=1'b0;
#10 a=8'b00000011;b=8'b00000011;cin=1'b1;
#10 a=8'b11111111;b=8'b00000001;cin=1'b0;
#10 a=8'b11111111;b=8'b00000000;cin=1'b1;
#10 a=8'b11111111;b=8'b11111111;cin=1'b0;
#10 $stop;
end
endmodule
OUTPUT
DLATCH
Module
module dlatchm(le, d, q);
input le;
input d;
output q;
reg q;
always @(le or d)
begin
if (le)
q<=d;
end
endmodule
TEST BENCH
module dlatcht_v;
reg le;
reg d;
wire q;
dlatchm uut (
.le(le),
.d(d),
.q(q)
);
initial begin
d = 0;
le = 0;
end
always #3 le=~le;
always #5 d=~d;
initial #100 $stop;
endmodule
OUTPUT
D FLIPFLOP
Module
module dflipflopm(q, d, clk);
output q;
input d;
input clk;
reg q;
always @(posedge clk)
q=d;
endmodule
TEST BENCH
module dflipflopt_v;
reg d;
reg clk;
wire q;
dflipflopm uut (
.q(q),
.d(d),
.clk(clk)
);
initial begin
// Initialize Inputs
d = 0;
clk = 0;
end
always #3 clk=~clk;
always #5 d=~d;
initial #100 $stop;
endmodule
OUTPUT
T FLIPFLOP
Module
module tflipflop(t, clk, q);
input t;
input clk;
output q;
reg q;
initial q<=1'b0;
always @(posedge clk)
q<=q^t;
endmodule
TEST BENCH
module tflipflopt_v;
reg t;
reg clk;
wire q;
tflipflop uut (
.t(t),
.clk(clk),
.q(q)
);
initial begin
t = 0;
clk = 0;
#100;
end
always #3 clk=~clk;
always #5 t=~t;
initial #100 $stop;
endmodule
OUTPUT
SISO
Module
module serialinoutm(clk,clear,si,so);
input clk,si,clear;
output so;
reg so;
reg [3:0] tmp;
always @(posedge clk )
begin
if (clear)
tmp <= 4'b0000;
else
tmp <= tmp << 1;
tmp[0] <= si;
so = tmp[3];
end
endmodule
TEST BENCH
module serialinoutt_v;
reg clk;
reg clear;
reg si;
wire so;
serialinoutm uut (
.clk(clk),
.clear(clear),
.si(si),
.so(so)
);
initial begin
clk = 0;
clear = 0;
si = 0;
#5 clear=1'b1;
#5 clear=1'b0;
#10 si=1'b1;
#10 si=1'b0;
#10 si=1'b0;
#10 si=1'b1;
#10 si=1'b0;
#10 si=1'bx;
end
always #5 clk = ~clk;
initial #150 $stop;
endmodule
OUTPUT
SIPO
Module
module serialnparallout(clk,clear, si, po);
input clk, si,clear;
output [3:0] po;
reg [3:0] tmp;
reg [3:0] po;
always @(posedge clk)
begin
if (clear)
tmp <= 4'b0000;
else
tmp <= tmp << 1;
tmp[0] <= si;
po = tmp;
end
endmodule
TEST BENCH
module serialinparoutt_v;
reg clk;
reg clear;
reg si;
wire [3:0] po;
serialnparallout uut (
.clk(clk),
.clear(clear),
.si(si),
.po(po)
);
initial begin
clk = 0;
clear = 0;
si = 0;
#5 clear=1'b1;
#5 clear=1'b0;
#10 si=1'b1;
#10 si=1'b0;
#10 si=1'b0;
#10 si=1'b1;
#10 si=1'b0;
#10 si=1'bx;
end
always #5 clk = ~clk;
initial #150 $stop;
endmodule
OUTPUT
PIPO
Module
module parallelinparallelout(clk,clear, pi, po);
input clk,clear;
input [3:0] pi;
output [3:0] po;
wire [3:0] pi;
reg [3:0] po;
always @(posedge clk)
begin
if (clear)
po<= 4'b0000;
else
po <= pi;
end
endmodule
TEST BENCH
module parallelinparalleloutt_v;
reg clk;
reg clear;
reg [3:0] pi;
wire [3:0] po;
parallelinparallelout uut (
.clk(clk),
.clear(clear),
.pi(pi),
.po(po)
);
initial begin
clk = 0;
clear = 0;
pi = 0;
#5 clear=1'b1;
#5 clear=1'b0;
#10 pi=4'b1001;
#10 pi=4'b1010;
#10 pi=4'b1011;
#10 pi=4'b1110;
#10 pi=4'b1111;
#10 pi=4'b0000;
end
always #5 clk = ~clk;
initial #150 $stop;
endmodule
OUTPUT
UPCOUNTER
Module
module upcoyntert(clk, clear, q);
input clk;
input clear;
output [3:0] q;
reg [3:0] q;
always@(posedge clear or posedge clk)
begin
if(clear)
q <=4'b0000;
else
q <= q+1'b1;
end
endmodule
TEST BENCH
module upcountert_v;
reg clk;
reg clear;
wire [3:0] q;
upcoyntert uut (
.clk(clk),
.clear(clear),
.q(q)
);
initial begin
clk = 0;
clear = 0;
#5 clear=1'b1;
#5 clear=1'b0;
end
always #5 clk=~clk;
initial #200 $stop;
endmodule
OUTPUT
DOWNCOUNTER
Module
module downcounter(clk, clear, q);
input clk;
input clear;
output [3:0] q;
reg [3:0] q;
always@(posedge clear or posedge clk)
begin
if(clear)
q <=4'b1111;
else
q <= q-1'b1;
end
endmodule
TEST BENCH
module upcountert_v;
reg clk;
reg clear;
wire [3:0] q;
downcounter uut (
.clk(clk),
.clear(clear),
.q(q)
);
initial begin
clk = 0;
clear = 0;
#5 clear=1'b1;
#5 clear=1'b0;
end
always #5 clk=~clk;
initial #200 $stop;
endmodule
OUTPUT
UP-DOWNCOUNTER
Module
module updowncounterm(clk, clear, updown, q);
input clk;
input clear;
input updown;
output [3:0] q;
reg [3:0] q;
always@(posedge clear or posedge clk)
begin
if(clear)
q <=4'b0000;
else if(updown)
q <= q+1'b1;
else
q <= q-1'b1;
end
endmodule
TEST BENCH
module updowncountert_v;
reg clk;
reg clear;
reg updown;
wire [3:0] q;
updowncounterm uut (
.clk(clk),
.clear(clear),
.updown(updown),
.q(q)
);
initial begin
clk = 0;
clear = 0;
updown = 0;
#5 clear=1'b1;
#5 clear=1'b0;
#100 updown=1'b1;
end
always #5 clk=~clk;
initial #150 $stop;
endmodule
OUTPUT
ASYNCHRONOUS COUNTER
Module
module asynchronouscounter(clk, clear, q);
input clk;
input clear;
output [3:0] q;
reg [3:0] q;
always @(negedge clk or posedge clear)
q[0]<=~q[0];
always @(negedge q[0] or posedge clear)
q[1]<=~q[1];
always @(negedge q[1] or posedge clear)
q[2]<=~q[2];
always @(negedge q[2] or posedge clear)
begin
if(clear)
q <=4'b0000;
else
q[3]<=~q[3];
end
endmodule
TEST BENCH
module asynchronouscountert_v;
reg clk;
reg clear;
wire [3:0] q;
asynchronouscounter uut (
.clk(clk),
.clear(clear),
.q(q)
);
initial begin
clk = 0;
clear = 0;
#5 clear=1'b1;
#5 clear=1'b0;
end
always #5 clk=~clk;
initial #200 $stop;
endmodule
OUTPUT
PRBS
Module
module prbs(d, clk, reset, q);
input [3:0] d;
input clk;
input reset;
output [3:0] q;
reg [3:0]q;
reg [3:0]temp;
always @(clk)
begin
if(reset)
q=4'b0000;
else
begin
temp=d;
temp[3]=temp[0]^temp[3];
q=temp<<1;
end
end
endmodule
TEST BENCH
module prbst_v;
reg [3:0] d;
reg clk;
reg reset;
wire [3:0] q;
prbs uut (
.d(d),
.clk(clk),
.reset(reset),
.q(q)
);
initial begin
d = 0;
clk = 0;
reset = 0;
#10 d=4'b0000;
#10 d=4'b0001;
#10 d=4'b0010;
#10 d=4'b0011;
#10 d=4'b0100;
#10 d=4'b0101;
#10 d=4'b0110;
#10 d=4'b0111;
#10 d=4'b1000;
#10 d=4'b1001;
#10 d=4'b1010;
#10 d=4'b1011;
#10 d=4'b1100;
#10 d=4'b1101;
#10 d=4'b1110;
#10 d=4'b1111;
end
always #5 clk=~clk;
initial #180 $stop;
endmodule
OUTPUT
ACCUMULATOR
Module
module accu (in, acc, clk, reset);
input [7:0] in;
input clk, reset;
output [7:0] acc;
reg [7:0] acc;
always@(clk) begin
if(reset)
acc <= 8'b00000000;
else
acc <= acc + in;
end
endmodule
TEST BENCH
module accumt_v;
reg [7:0] in;
reg clk;
reg reset;
wire [7:0] acc;
accu uut (
.in(in),
.acc(acc),
.clk(clk),
.reset(reset)
);
initial begin
#5 reset<=1'b1;
#5 reset<=1'b0;
clk =1'b0;
in = 8'b00000001;
#50 in = 8'b00000010;
#50 in = 8'b00000011;
end
always #10 clk = ~clk;
initial#180 $stop;
endmodule
OUTPUT
RAM
Module
module ramm (clk, we, addr, din, dout);
input clk;
input we;
input [4:0] addr;
input [3:0] din;
output [3:0] dout;
reg [3:0] ram [31:0];
reg [3:0] dout;
always @(clk)
begin
if (we)
ram[addr] <= din;
else
dout <= ram[addr];
end
endmodule
TEST BENCH
module ramt_v;
reg clk;
reg we;
reg [4:0] addr;
reg [3:0] din;
wire [3:0] dout;
ramm uut (
.clk(clk),
.we(we),
.addr(addr),
.din(din),
.dout(dout)
);
initial begin
clk = 0;
we = 0;
addr = 0;
din = 0;
#10 we=1'b1;
#10 addr=5'b00001;din=4'b0001;
#10 addr=5'b00010;din=4'b0010;
#10 addr=5'b00011;din=4'b0011;
#10 addr=5'b00100;din=4'b0100;
#10 addr=5'b00101;din=4'b0101;
#10 addr=5'bxxxxx;din=4'bxxxx;
#10 we=1'b0;
#10 addr=5'b00001;
#10 addr=5'b00010;
#10 addr=5'b00011;
#10 addr=5'b00100;
#10 addr=5'b00101;
end
always #10 clk = ~clk;
initial #150 $stop;
endmodule
OUTPUT
Very informative post. Keep up the good work. I would really look forward to your other posts
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Panasonic - 14" Toughbook Notebook - 4 GB Memory - 500 GB Hard Drive (CF-53STLZYLM)